(1) Field of the Invention
The present invention relates to a building for manufacturing highly dense, most advanced integrated circuits that is designed to use localized clean rooms around each piece of processing equipment and methods for manufacturing integrated circuits.
(2) Description of the Prior Art
There continues to be a dramatic increase in the complexity of integrated circuits each year. As applications develop for memories, microprocessor and minicomputers there is an increasing demand for greater complexities, higher switching speeds, and smaller devices in the integrated circuits.
The manufacturing or fabrication building design for integrated circuits has not kept up with the progress of the technologies for the manufacture of integrated circuits. The shortcoming in design has involved the clean room in which the processing equipment for making the integrated circuits is located. The clean room is of utmost importance because airborne contamination particles cause defects in the integrated circuits to the point that there is zero yield from the manufacture.
The present designs for manufacturing or fabrication buildings for integrated circuits involve maintaining a clean room by air circulation and filtering equipment for the whole manufacturing area at the highest possible clean room class. The U.S. Federal Standard No. 209d maintains the definition of the Classes from Class 100,000 down to Class 1. The most desired clean room today is Class 10 or even Class 1 if that could be attainable. However, the ability to design buildings with clean rooms of such classes is difficult due to the requirement of human workers, a major source of particulate contamination in the clean room and the substantial construction cost of accomplishing such a design.
One approach to upgrade existing clean rooms to higher air cleanliness has been described in the paper "Defect Density Reduction in a Class 100 Fab Utilizing the Standard Mechanical Interface" by Stephen Titus et al published in November 1987 issue of Solid State Technology. The photoresist coater and mask aligner on the manufacturing floor were fitted with an environmental enclosures with laminar air flow which provides near Class 1 ambient directly above the wafer processing area, and a robotic interface. A sealed wafer carrier which isolates the cassette of wafers from the environment was used to move the wafers throughout the clean room except when the robotic interface removes the wafer cassette into the coater or mask aligner. The experiment was stated as successful in the publication. The use of these structures in a wafer-fabrication building is described in the paper "VTC's Submicron CMOS Factory" by Wilton Workman et al in Microcontamination, October 1987. However, there is no description of methods for mobility or the adding/removal of processing equipment in an easy or quick manner in either of these papers. There are patents describing the details of this system involving the wafer cassette pod and robotic interfaces which include U.S. Pat. No. 4,534,389; U.S. Pat. No. 4,674,936; U.S. Pat. No. 4,724,874; U.S. Pat. No. 4,781,511; and U.S. Pat. No. 4,826,360.